Synergy Quantum has unveiled a new portfolio of quantum-safe silicon IP cores designed for RISC-V-based system-on-chip (SoC) designs. This announcement, made on June 18, 2026, enables semiconductor companies, processor developers, and equipment manufacturers to integrate post-quantum cryptographic capabilities directly into ASICs, FPGAs, and embedded platforms.
Post-Quantum Cryptographic Integration
The IP portfolio combines post-quantum cryptographic acceleration with secure boot, hardware-bound identity, protected key handling, firmware verification, and device-attestation capabilities. It is designed for integration into RISC-V-based SoCs as dedicated security components, cryptographic coprocessors, or building blocks within a broader hardware root-of-trust subsystem. By placing quantum-safe cryptographic functions directly in silicon, the architecture improves performance, reduces dependence on software-only implementations, and provides stronger isolation for sensitive keys and intermediate cryptographic values.
Addressing the RISC-V Ecosystem
RISC-V is increasingly adopted across embedded systems, industrial platforms, communications infrastructure, defense electronics, automotive systems, and custom semiconductor designs. Many of these devices are expected to remain operational for years or decades, requiring security architectures capable of supporting the transition from classical cryptography to post-quantum security. Synergy Quantum's silicon IP portfolio helps RISC-V developers address this transition at the processor and SoC level, enabling key establishment, signature verification, secure boot, and device-trust operations as dedicated hardware functions within the chip. The architecture supports industry-standard SoC interconnects and processor-extension interfaces, allowing integration with existing RISC-V processors without a complete redesign.
Key Features of the IP Portfolio
- ML-KEM-based post-quantum key establishment
- ML-DSA-based post-quantum digital signatures
- SLH-DSA and LMS-based hash-signature architectures
- HQC-based algorithm diversity
- SHA-3 and Keccak cryptographic processing
- Ascon authenticated encryption
- Shared number-theoretic transform acceleration
- Secure and measured boot
- Post-quantum firmware-signature verification
- Hardware-enforced anti-rollback protection
- PUF-derived device identity
- DICE-style device attestation
- Protected key derivation and key sealing
- Hybrid classical and post-quantum operation
The IP can be configured according to performance, power, silicon-area, and security requirements, ranging from compact blocks for IoT devices to higher-throughput accelerators for telecom and data-center applications.
Configurable RISC-V Security Architecture
The portfolio combines programmable RISC-V control with dedicated cryptographic hardware, allowing security policies and protocol handling to be managed through software while computationally intensive operations execute in isolated hardware datapaths. It supports post-quantum key establishment, secure firmware updates, quantum-safe secure boot, device onboarding, remote attestation, hardware-protected signing, and secure communications. IP cores can be integrated individually or combined into a complete quantum-safe security subsystem.
Crypto Agility and Future-Proofing
The architecture supports crypto agility through reusable arithmetic engines, shared cryptographic datapaths, and programmable security control. Shared NTT and Keccak processing components reduce hardware duplication, and configurations can support controlled cryptographic updates and anti-rollback mechanisms, enabling a staged migration from classical to hybrid to fully post-quantum operation.
Protection Against Implementation Attacks
Synergy Quantum's IP includes options for constant-time execution, masked arithmetic, isolated generation of masking values, secure zeroisation, PUF-bound key derivation, and tamper-aware attestation, designed for hostile or mission-critical environments.
Target Applications and Ecosystem
The IP targets RISC-V processor and SoC developers, semiconductor manufacturers, FPGA developers, defense and aerospace companies, telecom equipment manufacturers, industrial vendors, automotive developers, IoT device makers, and cloud infrastructure providers. It complements the SynQ Silicon Trust Suite, offering a vertically integrated approach from quantum-safe hardware to enterprise trust services.
Quote from Leadership
Jay Oberai, Founder of Synergy Quantum, stated: 'RISC-V gives semiconductor developers the flexibility to build processors around their own requirements. Quantum-safe security must become a native silicon capability rather than an afterthought. Our IP cores help developers integrate post-quantum cryptography and hardware-rooted trust directly into the SoC architecture.'
Enabling Sovereign Semiconductor Development
Ownership of cryptographic silicon IP is increasingly important for governments and critical infrastructure. Synergy Quantum's development provides a foundation for locally controlled processors and secure devices, allowing customization according to national and sector-specific requirements.
About Synergy Quantum
Synergy Quantum develops quantum-secure platforms, cryptographic hardware, and semiconductor security IP for governments, semiconductor companies, and critical-infrastructure operators. Their work spans post-quantum cryptography, RISC-V-integrated IP, hardware roots of trust, and crypto-agile infrastructure. For more information, visit synergyquantum.in.
